Wang, Zheng.
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip [electronic resource] / - 1st ed. 2018. - XX, 197 p. 104 illus., 72 illus. in color. | Binding - Card Paper | - Computer Architecture and Design Methodologies, 2367-3478 . - Computer Architecture and Design Methodologies, .
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
9789811010736
EXTC Engineering
Performance and Reliability. Electronic Circuits and Devices.
621.3815
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip [electronic resource] / - 1st ed. 2018. - XX, 197 p. 104 illus., 72 illus. in color. | Binding - Card Paper | - Computer Architecture and Design Methodologies, 2367-3478 . - Computer Architecture and Design Methodologies, .
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
9789811010736
EXTC Engineering
Performance and Reliability. Electronic Circuits and Devices.
621.3815