| 000 -LEADER |
|---|
| fixed length control field |
a |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20201222110617.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
201222b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
AIKTC-KRRC |
| Transcribing agency |
AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
12857 |
| Author |
Surana, Priya |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Genetic Algorithm Based Optimized Circuit Elements Placement In VLSI Design |
| 250 ## - EDITION STATEMENT |
|---|
| Volume, Issue number |
Vol.5(2), Jul-Dec |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
New Delhi |
| Name of publisher, distributor, etc. |
Journals Pub |
| Year |
2019 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Pagination |
22-31p. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
The optimization of printed circuit board and placing the electronic components with effectively is a challenging task. However, this dissertation report presents minimization of wire-length and failure rates of the board arising irregular local heat accumulation. By understanding the literature related to the problem in this dissertation two approaches are proposed and developed using genetic algorithms. First approach is for optimizing the placement of electronic components. The proposed genetic algorithm based electronic component placement approach is implemented in python. Second approach uses two criteria to place components: power dissipation (the heat dissipation of the elements should not damage nearby elements) and the total length of interconnections (should be as small as possible). The second approach is implemented using Unity and C# script. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| 9 (RLIN) |
4619 |
| Topical term or geographic name entry element |
EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
2723 |
| Co-Author |
Kumar, Rakesh |
| 773 0# - HOST ITEM ENTRY |
|---|
| Place, publisher, and date of publication |
New Delhi Journals pub |
| Title |
International journal of VLSI design and technology |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| URL |
http://ecc.journalspub.info/index.php?journal=JVDT&page=article&op=view&path%5B%5D=1137 |
| Link text |
Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Articles Abstract Database |
