Digital systems design using verilog (Record no. 7625)
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| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190815164639.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 181030b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781305120747 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | AIKTC-KRRC |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | ENG |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Edition number | DDC23 |
| Classification number | 621.395 |
| Item number | ROT/JOH |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 4973 |
| Personal name | Roth, Charles H. |
| 245 ## - TITLE STATEMENT | |
| Title | Digital systems design using verilog |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Cengage Learning |
| Date of publication, distribution, etc. | 2016 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | x, 582p. |
| Other physical details | | Binding - Paperback | |
| Dimensions | 23*20 cm |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | DIGITAL SYSTEMS DESIGN USING VERILOG integrates coverage of logic design principles, Verilog as a hardware design language, and FPGA implementation to help electrical and computer engineering students master the process of designing and testing new hardware configurations. A Verilog equivalent of authors Roth and John's previous successful text using VHDL, this practical book presents Verilog constructs side-by-side with hardware, encouraging students to think in terms of desired hardware while writing synthesizable Verilog. Following a review of the basic concepts of logic design, the authors introduce the basics of Verilog using simple combinational circuit examples, followed by models for simple sequential circuits. Subsequent chapters ask readers to tackle more and more complex designs. |
| Expansion of summary note | 1. REVIEW OF LOGIC DESIGN FUNDAMENTALS. Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing. Tristate Logic and Busses. 2. INTRODUCTION TO VERILOG. Computer-Aided Design. Hardware Description Languages. Verilog Description of Combinational Circuits. Verilog Modules. Verilog Assignments. Procedural Assignments. Modeling Flip-Flops Using Always Block. Always Blocks Using Event Control Statements. Delays in Verilog. Compilation, Simulation, and Synthesis of Verilog Code. Verilog Data Types and Operators. Simple Synthesis Examples. Verilog Models for Multiplexers. Modeling Registers and Counters Using Verilog Always Statements. Behavioral and Structural Verilog. Constants. Arrays. Loops in Verilog. Testing Verilog Model. A Few Things to Remember. 3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES. Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs). 4. DESIGN EXAMPLES. BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers. 5. SM CHARTS AND MIRCOPROGRAMMING. State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines. 6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS. Implementing Functions in FPGAs. Implementing Functions Using Shannon''s Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing. 7. FLOATING-POINT ARITHMETIC. Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations. 8. ADDITIONAL TOPICS IN VERILOG. Verilog Functions. Verilog Tasks. Multi-Valued Logic and Signal Resolution. Built-in Primitives. User Defined Primitives. SRAM Model. Model for SRAM Read/Write System. Rise and Fall Delays of Gates. Named Association. Generate Statements. System Functions. Compiler Directives. File I/O Functions. Timing Check. 9. DESIGN OF A RISC MICROPROCESSOR. The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model. 10. HARDWARE TESTING AND DESIGN FOR TESTABILITY. Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundary Scan. Built-In Self-Test. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://www.cengagebrain.com/cgi-wadsworth/course_products_wp.pl?fid=M20b&product_isbn_issn=9781305120747&token= |
| Public note | Student Companion Site |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Text Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Date last checked out | Cost, replacement price | Price effective from | Koha item type |
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| Reference | School of Engineering & Technology | School of Engineering & Technology | General Stacks | 2018-10-30 | 2 | 12027.20 | 2 | 621.395 ROT/JOH | E14547 | 2025-01-29 | 2024-07-29 | 15034.00 | 2018-10-30 | Text Books |