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OSt |
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20190319120324.0 |
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190319b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
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AIKTC-KRRC |
| Transcribing agency |
AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| 9 (RLIN) |
8144 |
| Author |
S, Ram Vishnu |
| 245 ## - TITLE STATEMENT |
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| Title |
Common mode scan based BIST for stuck-at-fault and path delay fault |
| 250 ## - EDITION STATEMENT |
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| Volume, Issue number |
Vol, 8(2), May-August |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Place of publication, distribution, etc. |
New Delhi |
| Name of publisher, distributor, etc. |
STM Journals |
| Year |
2018 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Pagination |
72-78p. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc. |
Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach between external testing and built-in self-test (BIST) is analyzed. The proposed method is based on weighted pseudorandom testing which uses a novel approach for compressing, and storing the weight sets. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at speed test using existing practical design-for-testability structures, such as scan design. In this work, a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The approach provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over existing methods. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| 9 (RLIN) |
4619 |
| Topical term or geographic name entry element |
EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
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| 9 (RLIN) |
8145 |
| Co-Author |
T. Yasodha |
| 773 0# - HOST ITEM ENTRY |
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| Place, publisher, and date of publication |
Noida STM Journals |
| Title |
Journal of VLSI design tools & technology (JoVDTT) |
| International Standard Serial Number |
2321–6492 |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
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| URL |
http://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/759 |
| Link text |
Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
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| Koha item type |
Articles Abstract Database |
