Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
By: Indira P
.
Contributor(s): Kamaraju M.
Publisher: New Delhi STM Journals 2019Edition: Vol.9(1), Jan-Apr.Description: 1-14p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest counterpart in implementing the pipeline technique, the occupied area of our model is reduced by 25%; and leads speed by 52%. The simulation and synthesis is carried out by the Xilinx platform with supported MATLAB graphs to describe the relationship between various parameters.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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School of Engineering & Technology Archieval Section | Not for loan | 2020115 |
Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest counterpart in implementing the pipeline technique, the occupied area of our model is reduced by 25%; and leads speed by 52%. The simulation and synthesis is carried out by the Xilinx platform with supported MATLAB graphs to describe the relationship between various parameters.
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