Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode
By: Singhal, Srishti
.
Contributor(s): Nagpal. Sushant.
Publisher: New Delhi STM Journals 2019Edition: Vol.9(1), Jan-Apr.Description: 15-21p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Traditional design techniques used in VLSI are in voltage mode, but these have drawbacks like low bandwidth, non-linearity and less gain. Current conveyors act similar to operational amplifiers but are advantageous over older VLSI design techniques because of high bandwidth-gain product, reduced power consumption etc. This paper consists of two parts: circuit diagram of current conveyor (which is a three terminal analog device) is discussed first and its working is analyzed, followed by the discussion on design of a universal active filter using current conveyor. If various bias currents are varied in active filter design across the passive components, the expected low-pass, high-pass and band-pass responses are obtained. This experiment was done in 45 nm CMOS technology using Cadence Virtuoso.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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School of Engineering & Technology Archieval Section | Not for loan | 2020116 |
Traditional design techniques used in VLSI are in voltage mode, but these have drawbacks like low bandwidth, non-linearity and less gain. Current conveyors act similar to operational amplifiers but are advantageous over older VLSI design techniques because of high bandwidth-gain product, reduced power consumption etc. This paper consists of two parts: circuit diagram of current conveyor (which is a three terminal analog device) is discussed first and its working is analyzed, followed by the discussion on design of a universal active filter using current conveyor. If various bias currents are varied in active filter design across the passive components, the expected low-pass, high-pass and band-pass responses are obtained. This experiment was done in 45 nm CMOS technology using Cadence Virtuoso.
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