Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits
By: Yadav, Karishma
.
Contributor(s): Khanna, Vandana.
Publisher: New Delhi STM Journals 2019Edition: Vol.9(1), Jan-Apr.Description: 38-43p.Online resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: The growth in technology has increased the usage of additional components on a single chip. This increased number of components on a single chip increases the significant amount of power dissipation and this causes the major challenge for the today’s circuit designers. There are several techniques in VLSI field which help to reduce power dissipations. This paper has analytical analysis of different low power techniques on CMOS inverter and NAND circuits; significant amount of power reduction in these circuits designed in 180 nm have been achieved.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
|
School of Engineering & Technology Archieval Section | Not for loan | 2020118 |
The growth in technology has increased the usage of additional components on a single chip. This increased number of components on a single chip increases the significant amount of power dissipation and this causes the major challenge for the today’s circuit designers. There are several techniques in VLSI field which help to reduce power dissipations. This paper has analytical analysis of different low power techniques on CMOS inverter and NAND circuits; significant amount of power reduction in these circuits designed in 180 nm have been achieved.
Click on an image to view it in the image viewer
There are no comments for this item.