Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB
By: Turaka, Rajasekhar
.
Contributor(s): Sai Ram, M. Satya.
Publisher: Noida STM Journals 2019Edition: Vol.9(3), Sep-Dec.Description: 1-11p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: We present “A Novel Conflict-Free Efficient Memory-Based Real Fast Fourier Transform (RFFT) using Urdhva Tiryagbhayam Butterfly”. In this paper different FFT lengths for address schemes are integrated that supports FFT processing which are used in diverse systems such as telecommunications. Address methods for various FFT lengths are coordinated in this paper to help FFT processing for different frameworks like broadcast communications. The memory bank and address can be produced by modulo and multiplication tasks of the deterioration digits. For both Single Power Point (SPP) and Non Single Power Point (NSPP) FFTs, high-radix calculation and parallel-processing method can be utilized to build the throughput. Moreover, a decomposition method, named High Radix Small Butterfly (HRSB), is designed to suit the high-radix algorithm. In the spot of HRSB, the Urdhva Tiryagbhyam Butterfly (UTB) is utilizes to increase the speed of multiplications. Both proposed and existed architecture will be implemented in various FPGA architectures to compare different parameters like area, power and delay. The throughput results are shown along with comparisons.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
|
School of Engineering & Technology Archieval Section | Not for loan | 2020-2021210 |
We present “A Novel Conflict-Free Efficient Memory-Based Real Fast Fourier Transform (RFFT) using Urdhva Tiryagbhayam Butterfly”. In this paper different FFT lengths for address schemes are integrated that supports FFT processing which are used in diverse systems such as telecommunications. Address methods for various FFT lengths are coordinated in this paper to help FFT processing for different frameworks like broadcast communications. The memory bank and address can be produced by modulo and multiplication tasks of the deterioration digits. For both Single Power Point (SPP) and Non Single Power Point (NSPP) FFTs, high-radix calculation and parallel-processing method can be utilized to build the throughput. Moreover, a decomposition method, named High Radix Small Butterfly (HRSB), is designed to suit the high-radix algorithm. In the spot of HRSB, the Urdhva Tiryagbhyam Butterfly (UTB) is utilizes to increase the speed of multiplications. Both proposed and existed architecture will be implemented in various FPGA architectures to compare different parameters like area, power and delay. The throughput results are shown along with comparisons.
Click on an image to view it in the image viewer
There are no comments for this item.