Investigations on decimal multipliers through novel partial product generators
By: Saha, Prabir
.
Contributor(s): Samanta, Puja.
Publisher: New York Springer 2022Edition: Vol.103(2), Apr.Description: 507-516p.Subject(s): Humanities and Applied SciencesOnline resources: Click here
In:
Journal of the institution of engineers (India): Series BSummary: Novel partial product generation scheme has been proposed for decimal multiplication where positional digit conversion methodology has been utilized. Moreover, through the proposed methodology 16 × 16 decimal digit multiplier has been introduced, where unconventional (4221) binary-coded decimal (BCD) number system has been focused. To implement the multiplication technique, multiplication digits have been converted into two decimal digits based on the corresponding bit weights. In addition with that, in partial product addition stage, optimized decimal digit compressors have been utilized. Besides that, mathematical expressions have been introduced for decimal ripple carry adder and through that final addition has been carried out. The proposed techniques also summarize the performances parameter matrices in terms of propagation delay, power, area and power delay product. Comparative analysis from its counterpart also has been addressed.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2022-1616 |
Novel partial product generation scheme has been proposed for decimal multiplication where positional digit conversion methodology has been utilized. Moreover, through the proposed methodology 16 × 16 decimal digit multiplier has been introduced, where unconventional (4221) binary-coded decimal (BCD) number system has been focused. To implement the multiplication technique, multiplication digits have been converted into two decimal digits based on the corresponding bit weights. In addition with that, in partial product addition stage, optimized decimal digit compressors have been utilized. Besides that, mathematical expressions have been introduced for decimal ripple carry adder and through that final addition has been carried out. The proposed techniques also summarize the performances parameter matrices in terms of propagation delay, power, area and power delay product. Comparative analysis from its counterpart also has been addressed.
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