On approach to optimize manufacturing of field-effect heterotransistors framework circuit of a combinational series-shunt switch to increase their integration rate: Influence mismatch-induced stress
By: Pankratov, E. L
.
Publisher: South Africa AkiNik Publications 2022Edition: Vol.3(2), Jul-Dec.Description: 83-104p.Subject(s): Electrical EngineeringOnline resources: Click here
In:
International journal of advances in electrical engineeringSummary: In this paper we introduce an approach to increase density of field-effect transistors in the framework
of a circuit of a combinational series-shunt switch. In the framework of the approach we consider
manufacturing the switch in a heterostructure with specific configuration. Several required areas of the
heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation
defects should by annealed framework optimized scheme. We also consider an approach to decrease
value of mismatch-induced stress in the considered heterostructure. We introduce an analytical
approach to analyze mass and heat transport in heterostructures during manufacturing of integrated
circuits with account mismatch-induced stress.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
|
School of Engineering & Technology Archieval Section | Not for loan | 2023-0873 |
In this paper we introduce an approach to increase density of field-effect transistors in the framework
of a circuit of a combinational series-shunt switch. In the framework of the approach we consider
manufacturing the switch in a heterostructure with specific configuration. Several required areas of the
heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation
defects should by annealed framework optimized scheme. We also consider an approach to decrease
value of mismatch-induced stress in the considered heterostructure. We introduce an analytical
approach to analyze mass and heat transport in heterostructures during manufacturing of integrated
circuits with account mismatch-induced stress.
Click on an image to view it in the image viewer
There are no comments for this item.