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Ternary based system for convolutional encoder

By: Rathi, Mayuri Chetan.
Contributor(s): Deshmukh, C. N.
Publisher: Haryana IOSR - International Organization of Scientific Research 2023Edition: Vol.13(4), Jul-Aug.Description: 36-41p.Subject(s): EXTC EngineeringOnline resources: Click here In: IOSR journal of VLSI and signal processing (IOSR-JVSP)Summary: Convolution coding has been used in communication systems including deep space communication and wireless communication. With demand for higher data rates beyond 10Gbps as per the recommendations of 60GHz communication standards processing speed of hardware and software modules need to further enhance to meet the requirements. VLSI circuits are designed with transistors sizing in nanometer range so as to operate at higher frequencies. With advances in semiconductor technology, transmitter and receiver circuits that meet the next generation wireless standards can be implemented on hardware that can operate at GHz frequency meeting the data rate greater than 10Gbps. Ternary computing uses trits to enable denser numerical encodings, support a fuzzy state, and give the cryptographer the opportunity to introduce new ciphering methods based on hardware primitives that can provide additional security. The focus is to search for new and better ternary convolutional codes with large free distance so more errors can be detected and corrected. The FEC code is used to secure data and information sent over the channel for storage as well as recover even in the presence of noise (errors). Interestingly, ternary architectures have been considered in computing and storage systems due to their higher radix economy and the three usable states for certain electromagnetic materials which have the potential to improve the performance of communication systems.
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Convolution coding has been used in communication systems including deep space communication
and wireless communication. With demand for higher data rates beyond 10Gbps as per the recommendations of
60GHz communication standards processing speed of hardware and software modules need to further enhance
to meet the requirements. VLSI circuits are designed with transistors sizing in nanometer range so as to operate
at higher frequencies. With advances in semiconductor technology, transmitter and receiver circuits that meet
the next generation wireless standards can be implemented on hardware that can operate at GHz frequency
meeting the data rate greater than 10Gbps. Ternary computing uses trits to enable denser numerical encodings,
support a fuzzy state, and give the cryptographer the opportunity to introduce new ciphering methods based on
hardware primitives that can provide additional security. The focus is to search for new and better ternary
convolutional codes with large free distance so more errors can be detected and corrected. The FEC code is
used to secure data and information sent over the channel for storage as well as recover even in the presence of
noise (errors). Interestingly, ternary architectures have been considered in computing and storage systems due
to their higher radix economy and the three usable states for certain electromagnetic materials which have the
potential to improve the performance of communication systems.

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