Low power and complexity implementation of the modified FFT with a new bit-slicing scheme
By: Shaik, Qadeer
.
Contributor(s): Keerthan, Harsha.
Publisher: USA Springer 2023Edition: Vol.104(6), Dec.Description: 1285-1302p.Subject(s): Humanities and Applied SciencesOnline resources: Click here
In:
Journal of the institution of engineers (India): Series BSummary: This paper talks over an efficient VLSI realization of the simplified arithmetic radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) technique. High performance FFT processors are used in several types of signal processing, and in order to fulfil these performance demands, the processor must be parallel and pipelined. This enhanced radix-2 method is used to create an improved ASIC design that implements a fully pipelined and parallel architecture for the hardware realization of a 64 point FFT. This scheme uses lesser multipliers by reducing bit-width of twiddle representation for improved power, area and speed with a considerable Signal to Noise Ratio (SNR). A reduction of 32.8% is obtained in the area occupied, 25.08% reduction in power consumption and 20.8% improvement in speed in comparison to the Cooley–Tukey FFT realization. Compared with serial implementation an improvement of 90% and parallel implementation an improvement of 58% in latency count is observed. The design is simulated using Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler with CMOS 180 nm technology.
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This paper talks over an efficient VLSI realization of the simplified arithmetic radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) technique. High performance FFT processors are used in several types of signal processing, and in order to fulfil these performance demands, the processor must be parallel and pipelined. This enhanced radix-2 method is used to create an improved ASIC design that implements a fully pipelined and parallel architecture for the hardware realization of a 64 point FFT. This scheme uses lesser multipliers by reducing bit-width of twiddle representation for improved power, area and speed with a considerable Signal to Noise Ratio (SNR). A reduction of 32.8% is obtained in the area occupied, 25.08% reduction in power consumption and 20.8% improvement in speed in comparison to the Cooley–Tukey FFT realization. Compared with serial implementation an improvement of 90% and parallel implementation an improvement of 58% in latency count is observed. The design is simulated using Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler with CMOS 180 nm technology.
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