System verilog for verification : A guide to learning the Testbench Language Features
By: Spear, Chris
.
Publisher: New Delhi Springer 2008Edition: 2nd.Description: xxxiii,429p. 23.8*16.3 cm | Binding- Hard Bound |.ISBN: 9788184895315.Subject(s): EXTC EngineeringDDC classification: 621.395 Online resources: Preview on Springer Summary: "As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs."
Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge
"It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first! The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!"
Stuart Sutherland, SystemVerilog Training Consultant, Sutherland HDL, Inc.
Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog’s verification constructs.
Testbenches are growing more complex. You need this book to keep up.
Includes nearly 500 code samples and 70 figures.
| Item type | Current location | Collection | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|
Text Books
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School of Engineering & Technology General Stacks | Circulation | 621.395 SPE (Browse shelf) | Available | E14558 | ||
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Text Books
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School of Engineering & Technology Reference Section | Reference | 621.395 SPE (Browse shelf) | Not For Loan | E13397 |
Browsing School of Engineering & Technology Shelves , Shelving location: Reference Section , Collection code: Reference Close shelf browser
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| 621.395 ROT Fundamentals of logic design | 621.395 ROT Fundamentals of logic design | 621.395 SED Textbook of Digital Electronics | 621.395 SPE System verilog for verification | 621.395 SZE VLSI technology | 621.395 TOK Digital Electronics | 621.395 VAH Digital design |
"As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs."
Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge
"It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first! The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!"
Stuart Sutherland, SystemVerilog Training Consultant, Sutherland HDL, Inc.
Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog’s verification constructs.
Testbenches are growing more complex. You need this book to keep up.
Includes nearly 500 code samples and 70 figures.
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