Design of three-stage pipelined floating point arithmetic operators
By: Shaikh, Shoeb Arif
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Contributor(s): Godbole, B. B.
Publisher: New Delhi STM Journals 2018Edition: Vol, 8(2), May-August.Description: 9-22p.Subject(s): EXTC EngineeringOnline resources: Click here
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Journal of VLSI design tools & technology (JoVDTT)Summary: Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer based approach. The RTL is developed in Verilog and design is implemented in Xilinx Virtex 7 series. The area and speed compared where mux based design claims lesser area then FSM based approach at the cost of marginal speed.
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School of Engineering & Technology Archieval Section | Not for loan | 2018143 |
Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer based approach. The RTL is developed in Verilog and design is implemented in Xilinx Virtex 7 series. The area and speed compared where mux based design claims lesser area then FSM based approach at the cost of marginal speed.
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