Comparative analysis of different SRAM cells architecture at 70 nm
By: Tiwari, Nidhi
.
Contributor(s): Neema, Vaibhav.
Publisher: New Delhi STM Journals 2018Edition: Vol, 8(2), May-August.Description: 33-41.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2018145 |
There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell.
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