High-Performance FinFET Based 8T SRAM with Enhanced Performance Parameters Using Self-Controllable Voltage level (SVL) Technique
By: Shrivastava, Vaibhav
.
Contributor(s): Saxena, Nikhil.
Publisher: New Delhi Journals Pub 2019Edition: Vol.5(1), Jan-Jun.Description: 16-24p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
International journal of microelectronics and digital integrated circuitsSummary: The scaling of standard single-gate bulk CMOS faces great challenge in the nanometer regime due to the severe short-channel effects (SCE) which causes significant increase in the leakage current. In this paper, a high-performance eight transistor (8T) SRAM has been proposed for reduction in leakage current and power consumption using double-gate FinFET with the proposed technique. Double gate FinFET has better SCEs performance compared to conventional CMOS. In this paper, a low-power 8T SRAM cell is designed with self-controllable voltage level (SVL) circuit for providing low power consumption and high performance. A self-controllable voltage level circuit can supply a maximum dc voltage when the load circuits are in active mode and it can also decrease the voltage supplied to a load circuit when the load circuit is in standby mode. This proposed technique significantly reduces the leakage current at a supply voltage of 0.9 V with a leakage reduction of value 0.46 nA in the leakage current of the circuit and provides high-performance SRAM cell. The following simulations have been done on SPICE tool on 32 nm technology.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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School of Engineering & Technology Archieval Section | Not for loan | 2020050 |
The scaling of standard single-gate bulk CMOS faces great challenge in the nanometer regime due to the severe short-channel effects (SCE) which causes significant increase in the leakage current. In this paper, a high-performance eight transistor (8T) SRAM has been proposed for reduction in leakage current and power consumption using double-gate FinFET with the proposed technique. Double gate FinFET has better SCEs performance compared to conventional CMOS. In this paper, a low-power 8T SRAM cell is designed with self-controllable voltage level (SVL) circuit for providing low power consumption and high performance. A self-controllable voltage level circuit can supply a maximum dc voltage when the load circuits are in active mode and it can also decrease the voltage supplied to a load circuit when the load circuit is in standby mode. This proposed technique significantly reduces the leakage current at a supply voltage of 0.9 V with a leakage reduction of value 0.46 nA in the leakage current of the circuit and provides high-performance SRAM cell. The following simulations have been done on SPICE tool on 32 nm technology.
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