Characterization of low power-low jitter digital PLL
- Vol, 8(2), May-August
- New Delhi STM Journals 2018
- 23-32p.
The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz phase locked loop in 180 nm CMOS technology. Phase noise of proposed design is –87.64 dBc/Hz at 1 MHz reference offset frequency. Total power dissipation of PLL is 6.92 mW and RMS jitter is 1.09 ns in locked condition.