Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits
- Vol.15(2), Apr
- Hyderabad IUP Publications 2022
- 42-58p.
In many arithmetic processors and digital signal processing applications, the binary adder is the primary computing block. Many electronic vendors have increased the demand for the least delay and minimum power consumption adders with multioperands to be consolidated in the present portable systems. In recent techniques, there has been a tendency regarding the expansion of programmable modules where processors utilize them to provide flexibility and execution. Mainly, neural network configurations are functionally verified by using software provinces. The utilization of the intended style of software implementation has many merits. The constraints of software perception of neural networks can be controlled using hardware implementation. The foremost interest of this paper is to realize the Exclusive-OR gate by Artificial Neural Network (ANN) using Multilayer Perceptron's (MLP) and activation functions as neuron output data values. The implementation results show that the MLP XOR and FA design attained notable refinement in contrast with the other described designs by achieving substantial savings in the total power dissipation and EDP.