000			a
999			_c10553 _d10553
003			OSt
005			20191216120505.0
008			191216b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_911202 _aSingh, Khoirom Johnson
245			_aComparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques
250			_aVol.8(1), Jan-Apr
260			_aNew Delhi _bSTM Journals _c2018
300			_a34-42p.
520			_aIn the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the best circuit design methods to reduce energy consumption in different operations. Adiabatic techniques make use of reversible logic in order to implement it on any circuit. A 4:2 priority encoder is designed as a combinational circuit. In this paper, ECRL (Efficient Charge Recovery logic) and CAL (Clocked Adiabatic Logic) are two adiabatic techniques implemented on Tanner EDA at 180 nm technology. The comparative analysis showed that power dissipation of ECRL is reduced by 16.038% as compared to CAL and conventional CMOS.
650		0	_94619 _aEXTC Engineering
700			_911204 _aSharan, Tripurari
773	0		_tJournal of VLSI design tools & technology (JoVDTT) _x2321–6492 _dNoida STM Journals
856			_uhttp://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/460 _yClick here
942			_2ddc _cAR