000			a
999			_c14696 _d14696
003			OSt
005			20210318102925.0
008			210318b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_913748 _aDeore, Sareeka.
245			_aAn Area Delay Optimized Carry-Select Adder
250			_aVol, (3),Sep-Dec
260			_aNew Delhi _bSTM Journals _c2018
300			_a10-14p.
520			_a arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to the presence of two Ripple Carry Adders (RCA) in the structure. To minimize the area of Regular SQRT CSLA, one of the RCAs was replaced by a Binary to Excess-1 Converter (BEC) with slight increase in delay. Many such techniques have provided to design variety of SQRT CSLAs by using Common Boolean Logic (CBL), First Addition Logic (FAL), Add-one circuit, Modified Reduced Logic Block (MRLB) etc. to achieve low area, delay and power. This work proposes a new design comprising of Carry generation (CG) and Carry Select (CS) to reduce the area as compared to the Regular SQRT CSLA and Modified SQRT CSLA using BEC. The proposed design is synthesized and simulated in Xilinx ISE design suite 14.2 and is implemented on Spartan 3E XC3S1600E-5-FG484 FPGA device. The comparison shows how the proposed SQRT CSLA is better than the existing regular SQRT CSLA and SQRT CSLA using BEC. The speed of proposed model is also enhanced for higher number of bits than the SQRT CSLA.
650		0	_94619 _aEXTC Engineering
773	0		_dNoida STM Journals _x2321–6492 _tJournal of VLSI design tools & technology (JoVDTT)
856			_uhttp://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/1277 _yClick Here
942			_2ddc _cAR