000			a
999			_c17832 _d17832
003			OSt
005			20221021113531.0
008			221021b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_918439 _aDhandapani, Vaithiyanathan
245			_aPerformance analysis of a high-speed high-precision dynamic comparator
250			_aVol.60(3), Mar
260			_aNew Delhi _bCSIR _c2022
300			_a238-245p.
520			_aComparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high- speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.
650		0	_94642 _aHumanities and Applied Sciences
700			_910347 _aMishra, Ashish
773	0		_tIndian journal of pure & applied physics (IJPAP) _dNew Delhi CSIR-NISCAIR _x0019-5596
856			_uhttp://nopr.niscpr.res.in/bitstream/123456789/59494/1/IJPAP%2060%283%29%20238-245.pdf _yClick here
942			_2ddc _cAR