000			a
999			_c20650 _d20650
003			OSt
005			20240203142703.0
008			240203b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_922869 _aMalhotra, Gayatri
245			_aFPGA accelerated parallel Hsclone GA for digital circuit configuration in CGP format
250			_aVol.104(5), Oct
260			_aUSA _bSpringer _c2023
300			_a1079-1089p.
520			_aThe embryonic fabric architecture has emerged recently for realizing the digital circuits having scope of self-repair with minimal resources. Digital circuit configuration data can be optimized using genetic algorithms (GA) in the design space. Further Cartesian Genetic programming (CGP) has evolved for improved representation of circuit configuration data. The design and implementation of PHsClone (Parallel Half-Sibling and Clone) GA are presented in this work for the purpose of producing design data in CGP format for digital systems realized on embryonic architecture. Due to computational complexity, GAs suffers from large convergence time, especially for evolving digital circuit design where search spaces are inherently large. Using parallel processing for HsClone algorithm on FPGA, configuration data or potential circuit solution can be generated at faster speed. The embryonic fabric on which the digital circuit is implemented can be self-repaired in case of fault. The CGP format of circuit configuration data enables the fault location at node or gate level. Also The CGP format of configuration data has advantage over LUT format as it does not increase linearly for larger modular circuits, e.g., 1-bit adder to 4-bit adder. The proposed PHsClone GA design is implemented on Xilinx Virtex-7. The PHsClone algorithm was tested on standard benchmark circuits like 1-bit adders and 2-bit comparators to build 4-bit adders and 8-bit comparators, as well as a safe mode sensing circuit used in-flight electronics. The simulation results show that a safe mode detection circuit can converge 37 times faster using four in-line PHsClone GA (parallel threads) than using a single HsClone GA. In comparison, a 1-bit adder can converge 10 times faster and a 2-bit comparator can converge 3 times faster.
650		0	_94642 _aHumanities and Applied Sciences
700			_922870 _aDuraiswamy, Punithavathi
773	0		_x2250-2106 _tJournal of the institution of engineers (India): Series B
856			_uhttps://link.springer.com/article/10.1007/s40031-023-00918-8 _yClick here
942			_2ddc _cAR