000			a
999			_c20790 _d20790
003			OSt
005			20240320110847.0
008			240320b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_914246 _aManoj Kumar
245			_aDesign of low-power CMOS VCO with three transistors NAND gate and MOS varactor
250			_aVol.104(4), Aug
260			_aUSA _bSpringer _c2023
300			_a851-858p.
520			_aA low-power VCO circuit design with varying NMOS load and 3-transistors NAND gate and is presented. VCO circuit is designed with 180 nm gate length. Tuning of the output frequency is controlled by deviation in voltage (VCT) from 1.8 to 2.7 V. Additionally, a change in output frequency is achieved with the change in reverse bias (VSB) and drain-source biasing (VTune) of NMOS load. Three-stages VCO with power supply and drain-source voltage tuning of NMOS varactor provides frequency from 1.308 to 1.891 GHz with circuit power varying from 0.390 to 1.573 mW. By utilizing the substrate tuning of NMOS varactor load, the circuit gives frequency varying from 1.308 to 1.808 GHz. Frequency changes from 1.308 to 1.564 GHz have been obtained by changing the reverse bias of NMOS load with different source/drain biasing. The tuning range of 36, 32, and 18% has been obtained. VCO provides a phase noise of −94.33 dBc/Hz @1 MHz and figure of merit (FoM) for the VCO is 160.74 dBc/Hz. The reported VCO circuit provides an improved output frequency range with reduced power consumption.
650		0	_94642 _aHumanities and Applied Sciences
773	0		_x2250-2106 _tJournal of the institution of engineers (India): Series B
856			_uhttps://link.springer.com/article/10.1007/s40031-023-00898-9 _yClick here
942			_2ddc _cAR