Design of a radiation-hardened SRAM cell using 16nm technology node
Rajat M.
Design of a radiation-hardened SRAM cell using 16nm technology node - Vol.14(4), Jul-Aug - Haryana IOSR - International Organization of Scientific Research 2024 - 36-43p.
Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space.
This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event
transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss.
This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative
study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to
SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple
interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually
injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and
98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has
been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model
(ASU-PTM), and the LTSpice software was used to carry out the simulations.
EXTC Engineering
Design of a radiation-hardened SRAM cell using 16nm technology node - Vol.14(4), Jul-Aug - Haryana IOSR - International Organization of Scientific Research 2024 - 36-43p.
Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space.
This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event
transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss.
This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative
study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to
SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple
interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually
injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and
98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has
been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model
(ASU-PTM), and the LTSpice software was used to carry out the simulations.
EXTC Engineering