Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques (Record no. 10552)
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| fixed length control field | a |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191216115049.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191216b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 11200 |
| Author | Dawarand, Aakriti |
| 245 ## - TITLE STATEMENT | |
| Title | Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.8(1), Jan-Apr |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | STM Journals |
| Year | 2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 30-33p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | In the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the best circuit design methods to reduce energy consumption in different operations. Adiabatic techniques make use of reversible logic in order to implement it on any circuit. A 4:2 priority encoder is designed as a combinational circuit. In this paper, ECRL (Efficient Charge Recovery logic) and CAL (Clocked Adiabatic Logic) are two adiabatic techniques implemented on Tanner EDA at 180 nm technology. The comparative analysis showed that power dissipation of ECRL is reduced by 16.038% as compared to CAL and conventional CMOS. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 11201 |
| Co-Author | Bal Krishan |
| 773 0# - HOST ITEM ENTRY | |
| International Standard Serial Number | 2321–6492 |
| Place, publisher, and date of publication | Noida STM Journals |
| Title | Journal of VLSI design tools & technology (JoVDTT) |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | http://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/460 |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 16/12/2019 | 2020482 | 16/12/2019 | 16/12/2019 | Articles Abstract Database |