Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB (Record no. 13893)
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| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20201231094053.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 201231b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 12883 |
| Author | Turaka, Rajasekhar |
| 245 ## - TITLE STATEMENT | |
| Title | Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.9(3), Sep-Dec |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Noida |
| Name of publisher, distributor, etc. | STM Journals |
| Year | 2019 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 1-11p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | We present “A Novel Conflict-Free Efficient Memory-Based Real Fast Fourier Transform (RFFT) using Urdhva Tiryagbhayam Butterfly”. In this paper different FFT lengths for address schemes are integrated that supports FFT processing which are used in diverse systems such as telecommunications. Address methods for various FFT lengths are coordinated in this paper to help FFT processing for different frameworks like broadcast communications. The memory bank and address can be produced by modulo and multiplication tasks of the deterioration digits. For both Single Power Point (SPP) and Non Single Power Point (NSPP) FFTs, high-radix calculation and parallel-processing method can be utilized to build the throughput. Moreover, a decomposition method, named High Radix Small Butterfly (HRSB), is designed to suit the high-radix algorithm. In the spot of HRSB, the Urdhva Tiryagbhyam Butterfly (UTB) is utilizes to increase the speed of multiplications. Both proposed and existed architecture will be implemented in various FPGA architectures to compare different parameters like area, power and delay. The throughput results are shown along with comparisons. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 12884 |
| Co-Author | Sai Ram, M. Satya |
| 773 0# - HOST ITEM ENTRY | |
| Place, publisher, and date of publication | Noida STM Journals |
| Title | Journal of VLSI design tools & technology (JoVDTT) |
| International Standard Serial Number | 2321–6492 |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | http://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/3705 |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Price effective from | Koha item type |
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| Dewey Decimal Classification | School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 31/12/2020 | 2020-2021210 | 31/12/2020 | 31/12/2020 | Articles Abstract Database |