Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits (Record no. 17496)
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| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220912131527.0 |
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| fixed length control field | 220912b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 17853 |
| Author | Pakkiraiah, C. |
| 245 ## - TITLE STATEMENT | |
| Title | Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.15(2), Apr |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Hyderabad |
| Name of publisher, distributor, etc. | IUP Publications |
| Year | 2022 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 42-58p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | In many arithmetic processors and digital signal processing applications, the binary adder is the primary computing block. Many electronic vendors have increased the demand for the least delay and minimum power consumption adders with multioperands to be consolidated in the present portable systems. In recent techniques, there has been a tendency regarding the expansion of programmable modules where processors utilize them to provide flexibility and execution. Mainly, neural network configurations are functionally verified by using software provinces. The utilization of the intended style of software implementation has many merits. The constraints of software perception of neural networks can be controlled using hardware implementation. The foremost interest of this paper is to realize the Exclusive-OR gate by Artificial Neural Network (ANN) using Multilayer Perceptron's (MLP) and activation functions as neuron output data values. The implementation results show that the MLP XOR and FA design attained notable refinement in contrast with the other described designs by achieving substantial savings in the total power dissipation and EDP. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 17854 |
| Co-Author | Satyanarayana, R. V. S. |
| 773 0# - HOST ITEM ENTRY | |
| Place, publisher, and date of publication | Hyderabad IUP Publications |
| Title | IUP journal of electrical and electronics engineering |
| International Standard Serial Number | 0974-1704 |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | https://www.iupindia.in/0422/Electrical%20and%20Electronics%20Engineering/Design_of_Low.asp |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 12/09/2022 | 2022-1564 | 12/09/2022 | 12/09/2022 | Articles Abstract Database |