Design of a radiation-hardened SRAM cell using 16nm technology node (Record no. 22574)
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| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20250403112327.0 |
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| fixed length control field | 250403b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 17494 |
| Author | Rajat M. |
| 245 ## - TITLE STATEMENT | |
| Title | Design of a radiation-hardened SRAM cell using 16nm technology node |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.14(4), Jul-Aug |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Haryana |
| Name of publisher, distributor, etc. | IOSR - International Organization of Scientific Research |
| Year | 2024 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 36-43p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space.<br/>This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event<br/>transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss.<br/>This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative<br/>study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to<br/>SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple<br/>interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually<br/>injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and<br/>98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has<br/>been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model<br/>(ASU-PTM), and the LTSpice software was used to carry out the simulations. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 17495 |
| Co-Author | Ram Rathan K.R. |
| 773 0# - HOST ITEM ENTRY | |
| International Standard Serial Number | 2319 – 4197 |
| Place, publisher, and date of publication | Gurgaon International Organization Of Scientific Research (IOSR) |
| Title | IOSR journal of VLSI and signal processing (IOSR-JVSP) |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | https://www.iosrjournals.org/iosr-jvlsi/papers/vol14-issue4/E14043643.pdf |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 03/04/2025 | 2025-0514 | 03/04/2025 | 03/04/2025 | Articles Abstract Database |