Digital design and verilog HDL fundamentals (Record no. 7622)
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| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190503113419.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 181029b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781420074154 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | AIKTC-KRRC |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | ENG |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Edition number | DDC23 |
| Classification number | 621.395 |
| Item number | CAV |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 4967 |
| Personal name | Cavanagh, Joseph |
| 245 ## - TITLE STATEMENT | |
| Title | Digital design and verilog HDL fundamentals |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Boca Raton |
| Name of publisher, distributor, etc. | CRC Press |
| Date of publication, distribution, etc. | 2008 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1147p. |
| Other physical details | | Binding - Paperback | |
| Dimensions | 24*17.8 cm |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Comprehensive and self contained, this tutorial covers the design of a plethora of combinational and sequential logic circuits using conventional logic design and Verilog HDL. Number systems and number representations are presented along with various binary codes. Several advanced topics are covered, including functional decomposition and iterative networks. A variety of examples are provided for combinational and sequential logic, computer arithmetic, and advanced topics such as Hamming code error correction. Constructs supported by Verilog are described in detail. All designs are continued to completion. Each chapter includes numerous design issues of varying complexity to be resolved by the reader. |
| Expansion of summary note | <br/>Table of Contents<br/>Number Systems, Number Representations, and Codes. Minimization of Switching Functions. Combinational Logic. Combinational Logic Design Using Verilog HDL. Computer Arithmetic. Computer Arithmetic Design Using Verilog HDL. Sequential Logic. Sequential Logic Design using Verilog HDL. Programmable Logic Devices. Digital and Analog Conversion. Magnetic Recording Fundamentals. Additional Topics in Digital Design. Appendix A: Event Queue. Appendix B: Verilog Project Procedure. Appendix C: Answers to Selected Problems. Index. |
| Uniform Resource Identifier | <a href="<br/>https://www.crcpress.com/Digital-Design-and-Verilog-HDL-Fundamentals/Cavanagh/p/book/9781420074154"><br/>https://www.crcpress.com/Digital-Design-and-Verilog-HDL-Fundamentals/Cavanagh/p/book/9781420074154</a> |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Not For Loan | Reference | School of Engineering & Technology | School of Engineering & Technology | Reference Section | 30/10/2018 | 2 | 1436.00 | 621.395 CAV | E14546 | 25/06/2025 | 1795.00 | 30/10/2018 | Books |