High-Performance FinFET Based 8T SRAM with Enhanced Performance Parameters Using Self-Controllable Voltage level (SVL) Technique (Record no. 9932)
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| fixed length control field | a |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191102100019.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191102b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 10240 |
| Author | Shrivastava, Vaibhav |
| 245 ## - TITLE STATEMENT | |
| Title | High-Performance FinFET Based 8T SRAM with Enhanced Performance Parameters Using Self-Controllable Voltage level (SVL) Technique |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.5(1), Jan-Jun |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Journals Pub |
| Year | 2019 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 16-24p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | The scaling of standard single-gate bulk CMOS faces great challenge in the nanometer regime due to the severe short-channel effects (SCE) which causes significant increase in the leakage current. In this paper, a high-performance eight transistor (8T) SRAM has been proposed for reduction in leakage current and power consumption using double-gate FinFET with the proposed technique. Double gate FinFET has better SCEs performance compared to conventional CMOS. In this paper, a low-power 8T SRAM cell is designed with self-controllable voltage level (SVL) circuit for providing low power consumption and high performance. A self-controllable voltage level circuit can supply a maximum dc voltage when the load circuits are in active mode and it can also decrease the voltage supplied to a load circuit when the load circuit is in standby mode. This proposed technique significantly reduces the leakage current at a supply voltage of 0.9 V with a leakage reduction of value 0.46 nA in the leakage current of the circuit and provides high-performance SRAM cell. The following simulations have been done on SPICE tool on 32 nm technology. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 10241 |
| Co-Author | Saxena, Nikhil |
| 773 0# - HOST ITEM ENTRY | |
| Title | International journal of microelectronics and digital integrated circuits |
| Place, publisher, and date of publication | New Delhi Journals Pub |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | http://ecc.journalspub.info/index.php?journal=JMDIC&page=article&op=view&path%5B%5D=1019 |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 02/11/2019 | 2020050 | 02/11/2019 | 02/11/2019 | Articles Abstract Database |