In the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the best circuit design methods to reduce energy consumption in different operations. Adiabatic techniques make use of reversible logic in order to implement it on any circuit. A 4:2 priority encoder is designed as a combinational circuit. In this paper, ECRL (Efficient Charge Recovery logic) and CAL (Clocked Adiabatic Logic) are two adiabatic techniques implemented on Tanner EDA at 180 nm technology. The comparative analysis showed that power dissipation of ECRL is reduced by 16.038% as compared to CAL and conventional CMOS.