000 04347nam a22005535i 4500
999 _c13128
_d13128
001 978-981-10-8554-3
003 DE-He213
005 20211217110958.0
008 180322s2018 si | s |||| 0|eng d
020 _a9789811085543
040 _cAIKTC-KRRC
041 _aENG
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aHaj-Yahya, Jawad.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
245 1 0 _aEnergy Efficient High Performance Processors
_h[electronic resource] :
_bRecent Approaches for Designing Green High Performance Computing /
250 _a1st ed. 2018.
264 1 _aSingapore :
_bSpringer Singapore :
_bImprint: Springer,
_c2018.
300 _aXIV, 165 p. 73 illus., 68 illus. in color.
_bCard Paper
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aComputer Architecture and Design Methodologies,
_x2367-3478
520 _aThis book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.
650 0 _aEXTC Engineering
_94619
653 _aProcessor Architectures.
653 _aElectronic Circuits and Devices.
700 1 _aMendelson, Avi.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
700 1 _aBen Asher, Yosi.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
700 1 _aChattopadhyay, Anupam.
_eauthor.
_0(orcid)0000-0002-8818-6983
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9789811085536
776 0 8 _iPrinted edition:
_z9789811085550
776 0 8 _iPrinted edition:
_z9789811341847
830 0 _aComputer Architecture and Design Methodologies,
_x2367-3478
856 4 0 _uhttps://doi.org/10.1007/978-981-10-8554-3
_zClick here to access eBook in Springer Nature platform. (Within Campus only.)
942 _cEBOOKS
_2ddc