000			a
999			_c17496 _d17496
003			OSt
005			20220912131527.0
008			220912b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_917853 _aPakkiraiah, C.
245			_aDesign of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits
250			_aVol.15(2), Apr
260			_aHyderabad _bIUP Publications _c2022
300			_a42-58p.
520			_aIn many arithmetic processors and digital signal processing applications, the binary adder is the primary computing block. Many electronic vendors have increased the demand for the least delay and minimum power consumption adders with multioperands to be consolidated in the present portable systems. In recent techniques, there has been a tendency regarding the expansion of programmable modules where processors utilize them to provide flexibility and execution. Mainly, neural network configurations are functionally verified by using software provinces. The utilization of the intended style of software implementation has many merits. The constraints of software perception of neural networks can be controlled using hardware implementation. The foremost interest of this paper is to realize the Exclusive-OR gate by Artificial Neural Network (ANN) using Multilayer Perceptron's (MLP) and activation functions as neuron output data values. The implementation results show that the MLP XOR and FA design attained notable refinement in contrast with the other described designs by achieving substantial savings in the total power dissipation and EDP.
650		0	_94619 _aEXTC Engineering
700			_917854 _aSatyanarayana, R. V. S.
773	0		_dHyderabad IUP Publications _tIUP journal of electrical and electronics engineering _x0974-1704
856			_uhttps://www.iupindia.in/0422/Electrical%20and%20Electronics%20Engineering/Design_of_Low.asp _yClick here
942			_2ddc _cAR