000			a
999			_c22574 _d22574
003			OSt
005			20250403112327.0
008			250403b xxu||||| |||| 00| 0 eng d
040			_aAIKTC-KRRC _cAIKTC-KRRC
100			_917494 _aRajat M.
245			_aDesign of a radiation-hardened SRAM cell using 16nm technology node
250			_aVol.14(4), Jul-Aug
260			_aHaryana _bIOSR - International Organization of Scientific Research _c2024
300			_a36-43p.
520			_aElectronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations.
650		0	_94619 _aEXTC Engineering
700			_917495 _aRam Rathan K.R.
773	0		_x2319 – 4197 _dGurgaon International Organization Of Scientific Research (IOSR) _tIOSR journal of VLSI and signal processing (IOSR-JVSP)
856			_uhttps://www.iosrjournals.org/iosr-jvlsi/papers/vol14-issue4/E14043643.pdf _yClick here
942			_2ddc _cAR