| 000 -LEADER |
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| fixed length control field |
a |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20220912150752.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
220912b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
AIKTC-KRRC |
| Transcribing agency |
AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| 9 (RLIN) |
14246 |
| Author |
Manoj Kumar |
| 245 ## - TITLE STATEMENT |
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| Title |
Low-power digitally controlled ring oscillator design with IMOS varactor tuning concept |
| 250 ## - EDITION STATEMENT |
|---|
| Volume, Issue number |
Vol.103(1), Feb |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
New York |
| Name of publisher, distributor, etc. |
Springer |
| Year |
2022 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Pagination |
1-11p. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.905@1 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| 9 (RLIN) |
4642 |
| Topical term or geographic name entry element |
Humanities and Applied Sciences |
| 773 0# - HOST ITEM ENTRY |
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| International Standard Serial Number |
2250-2106 |
| Title |
Journal of the institution of engineers (India): Series B |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
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| URL |
https://link.springer.com/article/10.1007/s40031-021-00621-6 |
| Link text |
Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Articles Abstract Database |
