Low-power digitally controlled ring oscillator design with IMOS varactor tuning concept
By: Manoj Kumar
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Publisher: New York Springer 2022Edition: Vol.103(1), Feb.Description: 1-11p.Subject(s): Humanities and Applied SciencesOnline resources: Click here
In:
Journal of the institution of engineers (India): Series BSummary: This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.905@1 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2022-1567 |
This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.905@1 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.
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