Performance analysis of a high-speed high-precision dynamic comparator (Record no. 17832)
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| fixed length control field | a |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20221021113531.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 221021b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 18439 |
| Author | Dhandapani, Vaithiyanathan |
| 245 ## - TITLE STATEMENT | |
| Title | Performance analysis of a high-speed high-precision dynamic comparator |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.60(3), Mar |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | CSIR |
| Year | 2022 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 238-245p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high- speed comparators have been introduced and reported by many researchers. This paper presents an examination of various kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage. All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage. The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4642 |
| Topical term or geographic name entry element | Humanities and Applied Sciences |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 10347 |
| Co-Author | Mishra, Ashish |
| 773 0# - HOST ITEM ENTRY | |
| Title | Indian journal of pure & applied physics (IJPAP) |
| Place, publisher, and date of publication | New Delhi CSIR-NISCAIR |
| International Standard Serial Number | 0019-5596 |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | http://nopr.niscpr.res.in/bitstream/123456789/59494/1/IJPAP%2060%283%29%20238-245.pdf |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent Location | Current Location | Shelving location | Date acquired | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 2022-10-21 | 2022-1894 | 2022-10-21 | 2022-10-21 | Articles Abstract Database |