Performance analysis of a high-speed high-precision dynamic comparator
By: Dhandapani, Vaithiyanathan
.
Contributor(s): Mishra, Ashish.
Publisher: New Delhi CSIR 2022Edition: Vol.60(3), Mar.Description: 238-245p.Subject(s): Humanities and Applied SciencesOnline resources: Click here
In:
Indian journal of pure & applied physics (IJPAP)Summary: Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-
speed comparators have been introduced and reported by many researchers. This paper presents an examination of various
kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly
concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the
stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of
transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage.
All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of
frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage.
The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that
there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2022-1894 |
Comparators are the key structure of any analog-to-digital-converters (ADCs). In recent days various low power and high-
speed comparators have been introduced and reported by many researchers. This paper presents an examination of various
kinds of comparators which is the second most generally utilized hardware block. The preamplifier stage is mainly
concerned with the power of the comparator, while latch structure defines the overall comparison speed. Hence, both the
stages of dynamic comparator need to be designed efficiently for achieving optimized performance. Proper optimization of
transistors in the comparator circuit helps to achieve low power dissipation and operate at a sufficiently low offset voltage.
All the circuit has been implemented and simulated using cadence virtuoso tool in 180 nm technology and uses a clock of
frequency 500 MHz to control the two stages of the comparator and provides rail to rail input common-mode voltage.
The power and delay of different comparator circuits have been analyzed. The results obtained from the analysis show that
there is a 32% reduction in power and the comparator design was 29% faster as compared to the conventional circuit.
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