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a |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20221228131336.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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221227b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
AIKTC-KRRC |
| Transcribing agency |
AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| 9 (RLIN) |
19381 |
| Author |
Gupta, Himanshu |
| 245 ## - TITLE STATEMENT |
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| Title |
Novel Memristor-Based SRAM Design with Improved Stability in Sub-Threshold Region |
| 250 ## - EDITION STATEMENT |
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| Volume, Issue number |
Vol, 103(6), Dec |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Place of publication, distribution, etc. |
New york |
| Name of publisher, distributor, etc. |
Springer |
| Year |
2022 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Pagination |
1863-1873p |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc. |
performance of Static Random Access Memory reduces drastically in terms of access energy and leakage power when it is operated in sub-threshold region. But, as the technology is advancing toward miniaturization it becomes important that the device should perform efficiently in sub-threshold region because when it operates in sub-threshold low power consumption and higher performance can be achieved. It becomes very challenging and tedious task to operate a SRAM cell in sub-threshold region. So, as to overcome this challenge a novel design of SRAM has been proposed in this work using memristors. This design not only provides better write stability but also consumes lesser power. In this paper, analysis of Write Static Noise Margin, Read Static Noise Margin and Power consumption have been performed for the novel design using different technologies i.e., 180 nm, 90 nm and 45 nm in Cadence Virtuoso. The write stability of this design has been analyzed for different supply voltages and different aspect ratios. To the best of author’s knowledge, this design of SRAM has not been proposed before. The RSNM and WSNM have been calculated for the design by using the butterfly method and a semi-analytical method for all the simulations at different technology nodes. It has been observed that both the values of WSNM follow each other very closely at all the technology nodes. The values have been compared with various memristor-based designs, and it is found that the proposed 4T4M design consumes much less power (~ × 15 times) than other proposed memristor-based memories. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| 9 (RLIN) |
4623 |
| Topical term or geographic name entry element |
Electrical Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
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| 9 (RLIN) |
19382 |
| Co-Author |
Bansal, Sandeep |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Journal of the institution of engineers (India): Series B |
| International Standard Serial Number |
2250-2106 |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
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| URL |
https://link.springer.com/article/10.1007/s40031-022-00774-y |
| Link text |
Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
|
| Koha item type |
Articles Abstract Database |
