Design of Energy Efficient Clock System (Record no. 9936)
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| fixed length control field | a |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191102111803.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191102b xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | AIKTC-KRRC |
| Transcribing agency | AIKTC-KRRC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 10252 |
| Author | Walunj, R. A. |
| 245 ## - TITLE STATEMENT | |
| Title | Design of Energy Efficient Clock System |
| 250 ## - EDITION STATEMENT | |
| Volume, Issue number | Vol.9(2), May-Aug |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Journals Pub |
| Year | 2019 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Pagination | 1-7p. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of device is an excellent option to have the ULP system. However, degraded performance and exacerbated variability are the major concerns of sub-threshold circuits. This work investigates the performance of CMOS clock system and hybrid (combination of CMOS and DTMOS) clock system in sub-threshold regime. The results indicate that the proposed hybrid clock system exhibit better output frequency, SLP, PDP, EDP and robustness compared to CMOS clock system. Keywords: Sub threshold, Voltage Controlled Oscillator (VCO), Current Starved VCO (CSVCO), Clock Distribution Network (CDN), Power Delay product (PDP), Energy Delay product (EDP), Slew Latency Product (SLP), Monte Carlo simulation |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| 9 (RLIN) | 4619 |
| Topical term or geographic name entry element | EXTC Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| 9 (RLIN) | 10255 |
| Co-Author | Pable, S. D. |
| 773 0# - HOST ITEM ENTRY | |
| International Standard Serial Number | 2321–6492 |
| Place, publisher, and date of publication | Noida STM Journals |
| Title | Journal of VLSI design tools & technology (JoVDTT) |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| URL | http://engineeringjournals.stmjournals.in/index.php/JoVDTT/article/view/2573 |
| Link text | Click here |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Articles Abstract Database |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent Location | Current Location | Shelving location | Date acquired | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| School of Engineering & Technology | School of Engineering & Technology | Archieval Section | 2019-11-02 | 2020054 | 2019-11-02 | 2019-11-02 | Articles Abstract Database |