Design of Energy Efficient Clock System
By: Walunj, R. A
.
Contributor(s): Pable, S. D.
Publisher: New Delhi Journals Pub 2019Edition: Vol.9(2), May-Aug.Description: 1-7p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of device is an excellent option to have the ULP system. However, degraded performance and exacerbated variability are the major concerns of sub-threshold circuits. This work investigates the performance of CMOS clock system and hybrid (combination of CMOS and DTMOS) clock system in sub-threshold regime. The results indicate that the proposed hybrid clock system exhibit better output frequency, SLP, PDP, EDP and robustness compared to CMOS clock system.
Keywords: Sub threshold, Voltage Controlled Oscillator (VCO), Current Starved VCO (CSVCO), Clock Distribution Network (CDN), Power Delay product (PDP), Energy Delay product (EDP), Slew Latency Product (SLP), Monte Carlo simulation
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School of Engineering & Technology Archieval Section | Not for loan | 2020054 |
Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of device is an excellent option to have the ULP system. However, degraded performance and exacerbated variability are the major concerns of sub-threshold circuits. This work investigates the performance of CMOS clock system and hybrid (combination of CMOS and DTMOS) clock system in sub-threshold regime. The results indicate that the proposed hybrid clock system exhibit better output frequency, SLP, PDP, EDP and robustness compared to CMOS clock system.
Keywords: Sub threshold, Voltage Controlled Oscillator (VCO), Current Starved VCO (CSVCO), Clock Distribution Network (CDN), Power Delay product (PDP), Energy Delay product (EDP), Slew Latency Product (SLP), Monte Carlo simulation
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