Fault Detection Attainment for Embedded Cores based on Software Test Routines
By: Puranik, Vishal Gangadhar
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Contributor(s): Shah, Dilip Devchand.
Publisher: New Delhi STM Journals 2018Edition: Vol.8(1), Jan-Apr.Description: 1-6p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: The test circuitry is designed in built-in-self-test (BIST) technique involves a system that applies the test signals and observes the corresponding system response. In this technique, the framework is embedded directly into the system hardware. The testing process performs efficiently, fastly and more economically than using an external test setup. Self-testing of embedded processors based on the test routines is an emerging method, since it employs a test resource partitioning technique instead of using external testers. In this paper, an improved methodology for embedded cores based on comprehension of their instruction set and register transfer (RT) level description is explained.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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School of Engineering & Technology Archieval Section | Not for loan | 2020478 |
The test circuitry is designed in built-in-self-test (BIST) technique involves a system that applies the test signals and observes the corresponding system response. In this technique, the framework is embedded directly into the system hardware. The testing process performs efficiently, fastly and more economically than using an external test setup. Self-testing of embedded processors based on the test routines is an emerging method, since it employs a test resource partitioning technique instead of using external testers. In this paper, an improved methodology for embedded cores based on comprehension of their instruction set and register transfer (RT) level description is explained.
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