Normal view MARC view ISBD view

High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator

By: Gandhi, Priyesh P.
Contributor(s): Devashrayee, N. M.
Publisher: New Delhi STM Journals 2018Edition: Vol.8(1), Jan-Apr.Description: 7-16p.Subject(s): EXTC EngineeringOnline resources: Click here In: Journal of VLSI design tools & technology (JoVDTT)Summary: This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed comparator has very wide dynamic range, low offset, low propagation delay with less power dissipation. The power consumption of the proposed comparator 43% less as compared to conventional comparators with improved dynamic range and very low offset voltage.
Tags from this library: No tags from this library for this title. Log in to add tags.
    average rating: 0.0 (0 votes)
Item type Current location Call number Status Date due Barcode Item holds
Articles Abstract Database Articles Abstract Database School of Engineering & Technology
Archieval Section
Not for loan 2020479
Total holds: 0

This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed comparator has very wide dynamic range, low offset, low propagation delay with less power dissipation. The power consumption of the proposed comparator 43% less as compared to conventional comparators with improved dynamic range and very low offset voltage.

There are no comments for this item.

Log in to your account to post a comment.

Click on an image to view it in the image viewer

Unique Visitors hit counter Total Page Views free counter
Implemented and Maintained by AIKTC-KRRC (Central Library).
For any Suggestions/Query Contact to library or Email: librarian@aiktc.ac.in | Ph:+91 22 27481247
Website/OPAC best viewed in Mozilla Browser in 1366X768 Resolution.

Powered by Koha